Archive for the ‘DAC’ Category

D1V3 & D1V33 upgrade to 96k Fs

Tuesday, November 3rd, 2009

 Since the SM5842 can only receive signal with maximum Fs at around 48kHz, it is not possible for D1V3 and D1V33 to receive 96k signal.  Due to that I have find one solution to do that using a AD1896 (or SRC4192) ASRC below.

DIR9001 –> AD1896 + 11.2896MHz XO –> SM5842 –> PCM63.

With above configuration, the input Fs can be from 32k till 96k while the output Fs from AD1896 is fixed at 44.1kHz.  AD1896 is set to Async mode with slave input mode and master output mode.  Both AD1896 and SM5842 is using master clock from the XO at 11.2896MHz.  Thus the jitter at SM5842 XTI will 100% depend on the quality of the XO.

Of course I can use a XO frequency of 12.288MHz to have a ouput Fs at 48kHz but I do not have this XO frequency on hand.  With higher Fs and later 8x over sample in the SM5842, the output noise after Jfet IV with single pole filter will be minimized.

Here is the picture of my implementation:

D1V3 & D1V33 upgrade to 24bit input mode

Thursday, October 29th, 2009

I remember there is one diyer of D1V3 told me that D1 is not able to receive true 24 bit digital data format.  The reason is that D1 has choosen to use 18 bit modes for CS8414 and SM5842.  In order for D1V3 and D1V33 to receive 24 bit data, I have tried out successfully to use the 24 bit Right Justified mode for both DIR9001 and SM5842.  Below is the details.

For DIR9001, set Pin 25 FMT0=H and Pin 26 FMT1=L means 24 bit Right Justified output data mode.  This is a easy setting by J1 short and J2 open on the DIR9001 converter board.

For SM5842,  the pin 5 IW1N and Pin 10 IW2N  has to be both Low (GND) for 24 bit data input mode right justified.  In the design of the pcb, there is no jumper setting for SM5842 IW2N (pin 10) which is always tie to +5V (High).  Thus the follow procedure has to be done to make the change to 24bit data input mode.

  1. Cut the trace on the bottom of the pcb on both sides of the pin 10 trace as shown.  Cut two line with 1mm width and remove copper in between as in the picture.  Check with ohmmeter for open circuit.
  2. Solder a wire from the Pin 10 of SM5842 to Pin 8 which is ground pin (thin blue wire).
  3. Connect a wire (thick green wire) from +5V supply of SM5842 to the jumper side as show in the pictures.  This is to ensure the jumpers has the +5V supply as usual.
  4. On component side, set J22 to 8414 (18bit) side, i.e. Pin 5 become Low (Ground).

FFT measurements show that the different between 16 and 20 bit signal noise floor is more than 12 db at -80dbFS input for PCM63 DAC.  This proved that the digital data input 24bit right justified mode is working!

For PCM1704, the lowest noise floor is about -132dbV with 24 bit -90dbFS data input.

FFT DAC D1V33 16 vs 20 bit PCM63

FFT DAC D1V33 16 vs 20 bit -80dbFS PCM63

DAC D1V33 63 vs 1704 at FS 24bit

FFT DAC D1V33 1704 at -90dbFS 24bit

Update Mar 13, 2010:

For PMD100 converter board, cut trace between pin 12 and 13.  Short the pin 13 to pin 14 (ground) – PMD100 set to 16 to 24 bit input mode with Left Justified.

Set jumper of DIR9001 J1 – open and J2 – short; this is to set Left Justified output mode for DIR9001.

*** Do not do below change for PCM63 user ***

If you want to change the PMD100 converter board to 24 bit ouput mode (for PCM1704), you have to set pin 10 from L (ground) to H (5V).  The problem with the converter board is that the top and bottom of pin 10 is shorted to ground plan.  Thus you have to cut both trace on top and bottom but it is impossible to modify if you have soldered the chip or IC socket! 

Short pin 10 to pin 11 if you can isolated the ground connection on pin 10.  Then you have 24 bit output mode.

PCM1704 to PCM63 Converter BD

Tuesday, October 27th, 2009

Since I have a PCM1702 to PCM63 converter board pcb, I have put a PCM1704 on same adaptor board for testing purposes.  The only difference is two supply pins +/-5V need to be reversed.  Thus I do cut trace and add two hard wires at the bottom of the board to fit the supply reverse for PCM1704 DAC chips.

For Capacitor, I use Panasonic FC and also Wima MKS film capacitor for supply decouple as in the pictures.

For PCM1704, the noise floor is a bit lower as you can see from the FFT measurement.

D1V33 FFT with PCM1704

D1V33 FFT with PCM63 lin

D1V3 + Squeezebox Classic (SB3)

Friday, September 11th, 2009

This is a modification of SB3 clock to sync to D1V3 on board super clock 11.2896MHz XO.

  1. Major improvement on D1V3 is to use a clean super clock for SM5842AP.
  2. Major problem is to connect the D1V3 super clock back to SB3.  Thus SB3 internal modifications are needed.  SMA coaxial cable is connected to pin 9 of HCU04 IC and ground.
  3. A separate 3.3V AMS1117 regulator is used for the CPLD and HCU04 ICs.  Sanyo OS-con and film cap are used for supply bypass.
  4. A linear 5V 1.5A regulator is used to replace the original switching adapter.

With this modification, the SB3 will not be able to play back other sampling frequencies file other than 44.1kHz!  Thus it is only good for CD playback now.

Some measurements:

SB3 SPDIF digital out FFT @ 1kHz

SB3 SPDIF digital out FFT @ 18kHz

D1V3 and SB3 FFT @ 1kHz (D1V3 analogy output)

D1V3 and SB3 FFT @ 18kHz (D1V3 analogy output)


Thursday, June 11th, 2009

This is D1V33 completed in April 2009 and currently is still on sales.

Price refer to “D1V33 BOM” and Kit details refer to “D1V33 Assembly Manual” below:


D1V33 Silk Top

D1V33 Circuit Diagrams

D1V33_BOM *Updated on Jan 15, 2010*

D1V33 Assembly Manual

D1V33 FFT 1

D1V33 FFT 2

D1V33 FFT with PCM1704